As the core computing chip of network equipment, network processor can complete the essential services such as routing lookup, high-speed packet processing, and QoS guarantee. Facing the transformation of network environment brought by ultra-high bandwidth and intelligent terminal, the design of the next generation network processor (NGNP) with high performance and evolution is a hot issue in the field of network communication, which is widely concerned by scholars. Combining the advantages of different chip architectures and high-speed services, NGNP has the characteristics of accelerating packet processing, dynamic configuration of hardware resources, and intelligent service application. In this study, the existing research is analyzed and compared from the design of NGNP which using new programmable technology, new network architecture oriented and for new high-performance service. The industrialization process of NGNP is summarized. Finally, the high performance evolvable network processor (HPENP) architecture is proposed. By introducing the hardware and software collaborative packet processing pipeline, multi-level cache and packet scheduling, resource management and programming interface, the details of HPENP design are given and a prototype system is developed and its performance is tested. In this study, the development direction and intelligent application scenario of autonomously controlled network processor architecture are confirmed, and the possible research direction in the future is discussed.