Parallelism Recognition Technology Based on Nested Loops Classifying
Author:
Affiliation:

  • Article
  • | |
  • Metrics
  • |
  • Reference [12]
  • |
  • Related [20]
  • | | |
  • Comments
    Abstract:

    Existing distributed memory parallelizing compiler systems are mostly developed based on sharedsystems. The parallelism recognition technologies of shared memory parallelizing compiler systems are suitable forOpenMP code generation. Their implementation is used to recognize all nested loops by the same technology, sothat the parallelism cannot be efficiently explored when applying them to distributed memory parallelizing compilersystems. Thus, this paper proposes some parallelism recognition technologies suitable for the MPI code generationfor distributed memory parallelizing compiler systems by classifying the nested loops according to their structures.To solve these problems, a new classification method of nested loops is proposed, according to the structure ofnested loops and characteristics of MPI parallel program. Corresponding parallelism recognition technologies fordifferent nested loops are also presented, respectively. The experimental results show that compared with thedistributed memory parallelizing compiler systems that used existing parallelism recognition technologies, thecompiler systems, which use the proposed classification method and the corresponding recognition technologies,can more efficiently recognize parallel nested loops in the benchmark programs, and the performance speedup of theMPI codes automatically increased to more than 20%.

    Reference
    [1] Zou DQ, He LG, Jin H, Chen XG. CRBAC: Imposing multi-grained constraints on the RBAC model in the multi-application environment. Journal of Network and Computer Applications, 2009,32(2):402 411. [doi: 10.1016/j.jnca.2008.02.015]
    [2] Hall MW, Amarasinghe SP, Murphy BR, Liao S, Lam MS. Interprocedural parallelization analysis in SUIF. ACM Trans. on Programming Languages and Systems, 2005,27(4):662 731. [doi: 10.1145/1075382.1075385]
    [3] Lin M, Yu ZY, Zhang D, Zhu YM, Wang SY, Dong Y. Retargeting the Open64 compiler to PowerPC processor. In: Proc. of the Embedded Software and Systems Symposia. San Francisco: IEEE Computer Society Press, 2008. 152 157. http://doi.ieeecomputer society.org/10.1109/ICESS.Symposia.2008.69 [doi: 10.1109/ICESS.Symposia.2008.69]
    [4] Kwon D, Han S, Kim H. MPI backend for an automatic parallelizing compiler. In: Proc. of the 14th Int’l Symp. on Parallel Architectures, Algorithms and Networks. San Francisco: IEEE Computer Society Press, 1999. 152 157. http://doi.ieeecomputer society.org/10.1109/ISPAN.1999.778932 [doi: 10.1109/ISPAN.1999.778932]
    [5] Ding Y, Kandemir M, Irwin MJ, Raghavan P. Adapting application mapping to systematic within-die process variations on chip multiprocessors. Lecture Notes in Computer Science, 2009,5409(1):231 247. [doi: 10.1007/978-3-540-92990-1_18]
    [6] Ferner CS. The paraguin compiler—Message-Passing code generation using SUIF. In: Proc. of the IEEE SoutheastCon 2002. Piscataway: IEEE Press, 2002. 1 6. [doi: 10.1109/.2002.995545]
    [7] Allen R, Kennedy K. Optimizing Compilers for Modern Architectures: A Dependence-Based Approach. Morgan Kaufmann Publishers, 2001.
    [8] Hu CJ, Li J, Wang J, Yao GL, Li YH, Ding L, Li JJ. Communication set generation for a special case of irregular parallel applications. Chinese Journal of Computers, 2008,31(1):120 126 (in Chinese with English abstract).
    [9] BastoulC, Cohen A, Girbal S, Sharma S, Temam O. Putting polyhedral loop transformations to work. In: Rauchwerger L, ed. Proc. of the 16th Int’l Workshop on Languages and Compilers for Parallel Computing. Berlin: Springer-Verlag, 2004. 209 225. [doi: 10.1007/978-3-540-24644-2_14]
    [10] Hoefler T, Lumsdaine A, Dongarra J. Towards efficient map reduce using MPI. In: Ropo M, Westerholm J, Dongarra J, eds. Proc. of the 16th European PVM/MPI Users’ Group Meeting on Recent Advances in Parallel Virtual Machine and Message Passing Interface. Berlin: Springer-Verlag, 2009. 240 249. [doi: 10.1007/978-3-642-03770-2_30]
    [11] Girbal S, Vasilache N, Bastoul C, Cohen A, Sigler DPM, Temam O. Semi-Automatic composition of loop transformations for deep parallelism and memory hierarchies. Int’l Journal of Parallel Programming, 2006,34(3):261 317. [doi: 10.1007/s10766-006-0012-3]
    [12] Roy S, Srikant YN. Partial flow sensitivity. Lecture Notes in Computer Science, 2007,4873(1):245 256. [doi: 10.1007/978-3-540-77220-0_25]
    Cited by
    Comments
    Comments
    分享到微博
    Submit
Get Citation

赵捷,赵荣彩,丁锐,黄品丰.基于嵌套循环分类的并行识别技术.软件学报,2012,23(10):2695-2704

Copy
Share
Article Metrics
  • Abstract:3656
  • PDF: 6397
  • HTML: 0
  • Cited by: 0
History
  • Received:July 26,2011
  • Revised:January 16,2012
  • Online: September 30,2012
You are the first2038035Visitors
Copyright: Institute of Software, Chinese Academy of Sciences Beijing ICP No. 05046678-4
Address:4# South Fourth Street, Zhong Guan Cun, Beijing 100190,Postal Code:100190
Phone:010-62562563 Fax:010-62562533 Email:jos@iscas.ac.cn
Technical Support:Beijing Qinyun Technology Development Co., Ltd.

Beijing Public Network Security No. 11040202500063