An in-order queuing (IOQ) PPS architecture proposed in this paper uses a small fixed-size buffer in the demultiplexor to distribute traffic equally among switch planes, with central combined input-and-output queuing (CIOQ) switch planes under the control of a single scheduler that applies the same matching at each of the parallel switch planes during each cell slot. This operation is called synchronous scheduling. It is proved that the round robin demultiplexing algorithm along with synchronous scheduling guarantees cells of a flow can be read in order from the output queues of the switch planes. Furthermore, by using a synchronous scheduling called strict longest queue first (SLQF) algorithm this scheme reduces considerably not only the amount of state information required by the scheduler, but the communication overhead required to achieve cell reordering. Compared with existing PPS designs, IOQ PPS (in-order queuing parallel packet switch) is more practical to implement in hardware because of its simple implementation mechanisms, as the experimental results demonstrate, and it offers the best delay performance.