Design and Implementation of a VHDL-C++ Translator
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    Abstract:

    VHDL (VHSIC (very high speed integrated circuit) hardware description language) is a language for the description of digital hardware system, and C++ is a programming language for coding sequential statements. VHDL compiled simulators use sequential C++ language to model circuits in VHDL with concurrent characterization. An object-oriented method of translating concurrent VHDL codes into sequential C++ codes is presented in this paper. This method takes the object-oriented characteristic of the two language into consideration and makes the translation very smooth. Using class of C++ to model entity, archiecture and process of VHDL, and combining with a simulation kernel, it accomplishes the job of modeling concurrent actions using sequential statements. By this method, VHDL codes can be translated to C++ codes with the same function, and the C++ codes then can be compiledand linked with simulation kernel code to an executable file, which is the compiled simulator. The execution of this file is the simulation of the design of VHDL. This method is well-structured and easily-extended, and the simulator got by this method is more efficient than the traditional one. This method has been successfully applied in the simulator. The performance and efficiency of the method are verified at the end of of this paper.

    Reference
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    [2] Ganguly, N. HSIM1 and HSIM2: object oriented algorithms for VHDL simulation. In: Proceedings of the 7th International Conference on VLSI Design. IEEE Computer Society Press, 1994. 175~178.
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    [7] Darmont, J. DESP-C++: a discrete-event simulation package for C++. Software-Practice and Experience, 2000,30(1):37~60.
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吴清平,刘明业. VHDL-C++翻译器设计与实现.软件学报,2002,13(11):2201-2207

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History
  • Received:March 13,2001
  • Revised:June 21,2001
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