• Article
  • | |
  • Metrics
  • |
  • Reference [9]
  • |
  • Related [20]
  • | | |
  • Comments
    Abstract:

    The CPU/FPGA hybrid architecture is a popular reconfigurable computing architecture. In order to ease the use of FPGA, a hardware thread approach is proposed, and a hardware thread executing mechanism is designed to make use of the reconfigurable resources. Software thread and hardware thread can be executed in parallel while computation-intensive tasks are assigned to hardware threads and control-intensive tasks are assigned to software threads. Simics simulator is adopted to simulate a hybrid architecture platform, on which software and hardware multithreading DES, MD5SUM and MergeSort algorithms are evaluated. The results show that the average speedup is 2.30, and it proves that the approach explored the performance of CPU/FPGA hybrid architecture efficiently.

    Reference
    [1] Mishra SM, Cabric D, Chang C, Willkomm D, van Schewick B, Wolisz A, Brodersen RW. A real time cognitive radio testbed for physical and link layer experiments. In: Proc. of the 2005 IEEE Symp. on New Frontiers in Dynamic Spectrum Access Networks. 2005. 562–567.
    [2] Lin EC, Yu K, Rutenbar RA, Chen T. A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. In: Proc. of the 15th ACM/SIGDA Int’l Symp. on Field Programmable Gate Arrays. 2007. 60–68.
    [3] Ortigosa EM, Ortigosa PM, Ca?as A, Ros E, Agís R, Ortega J. FPGA implementation of multi-layer perceptrons for speech recognition. In: Field-Programmable Logic and Applications. Berlin: Springer-Verlag, 2003. 1048?1052.
    [4] Dydel S, Bala P. Large scale protein sequence alignment using fpga reprogrammable logic devices. In: Field Programmable Logic and Application. Berlin: Springer-Verlag, 2004. 23–32.
    [5] So HK. BORPH: An Operating System for FPGA-Based Reconfigurable Computers [Ph.D. Thesis]. Berkeley: University of California, 2007.
    [6] Stitt G, Vahid F. Thread warping: A framework for dynamic synthesis of thread accelerators. In: Proc. of the 5th IEEE/ACM Int’l Conf. on Hardware/Software Codesign and System Synthesis. 2007. 93–98.
    [7] Anderson E, Agron J, Peck W, Stevens J, Baijot F, Komp E, Sass R, Andrews D. Enabling a uniform programming model across the software/hardware boundary. In: Proc. of the 14th Annual IEEE Symp. on Field-Programmable Custom Computing Machines. 2006. 89–98.
    [8] Estrin G. Reconfigurable computer origins: The ucla fixed-plusvariable (f+v) structure computer. IEEE Annals of the History of Computing, 2002,24(4):3–9.
    [9] Compton K, Hauck S. Reconfigurable computing: A survey of systems and software. ACM Computer Surveys, 2002,34(2): 171–210.
    Cited by
    Comments
    Comments
    分享到微博
    Submit
Get Citation

陈天洲,严力科,胡 威,马吉军. CPU/FPGA混合架构上的硬件线程加速方法.软件学报,2009,20(zk):15-22

Copy
Share
Article Metrics
  • Abstract:5395
  • PDF: 6439
  • HTML: 0
  • Cited by: 0
History
  • Received:July 01,2008
  • Revised:April 02,2009
You are the first2032519Visitors
Copyright: Institute of Software, Chinese Academy of Sciences Beijing ICP No. 05046678-4
Address:4# South Fourth Street, Zhong Guan Cun, Beijing 100190,Postal Code:100190
Phone:010-62562563 Fax:010-62562533 Email:jos@iscas.ac.cn
Technical Support:Beijing Qinyun Technology Development Co., Ltd.

Beijing Public Network Security No. 11040202500063