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    Abstract:

    The CPU/FPGA hybrid architecture is a popular reconfigurable computing architecture. In order to ease the use of FPGA, a hardware thread approach is proposed, and a hardware thread executing mechanism is designed to make use of the reconfigurable resources. Software thread and hardware thread can be executed in parallel while computation-intensive tasks are assigned to hardware threads and control-intensive tasks are assigned to software threads. Simics simulator is adopted to simulate a hybrid architecture platform, on which software and hardware multithreading DES, MD5SUM and MergeSort algorithms are evaluated. The results show that the average speedup is 2.30, and it proves that the approach explored the performance of CPU/FPGA hybrid architecture efficiently.

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陈天洲,严力科,胡 威,马吉军. CPU/FPGA混合架构上的硬件线程加速方法.软件学报,2009,20(zk):15-22

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History
  • Received:July 01,2008
  • Revised:April 02,2009
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