SPARC架构下低时延微内核进程间通信设计
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TP316

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国家自然科学基金青年基金(62202292); 上海市科技创新行动计划(22511101102)


Low-latency Microkernel IPC Design for SPARC Architecture
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    摘要:

    微内核系统将系统服务迁移到用户态运行, 因其架构隔离性而具有高可靠性的优势, 这一优势与航天领域的需求相契合. SPARC架构的处理器被广泛应用于航天飞船、卫星载荷以及星球车的控制设备上, 而该架构的寄存器窗口机制会影响微内核进程间通信(inter-process communication, IPC)的性能, 其核间中断(inter-processor interrupt, IPI)也会严重影响跨核IPC的效率. IPC作为微内核系统的关键机制, 对微内核上应用程序的整体性能十分重要. 基于对SPARC寄存器窗口机制的观察, 重新设计实现寄存器组机制, 由系统内核对寄存器窗口进行分配和管理, 并藉此实现SPARC架构上的BankedIPC. 同时, 在多核场景下, 针对SPARC上IPI性能较差的问题, 设计实现FlexIPC以优化跨核IPC的性能. 使用这些方法对自研微内核ChCore上已经实现的通用的同步IPC进行优化. 测试表明, 优化后SPARC上微内核的IPC平均性能提升至原来的2倍, 应用性能提升最高可达15%.

    Abstract:

    Microkernels migrate system services to user mode. Thanks to the isolated framework, microkernels are superior in high reliability, which meets the needs of the aerospace field. SPARC processors are widely applied on the control equipment of spacecraft, satellite payloads, and planetary vehicles. The register window mechanism of SPARC will affect the performance of inter-process communication (IPC) on microkernels. Besides, its inter-processor interrupt (IPI) also seriously affects the efficiency of cross-core IPC. As a key mechanism, IPC is vital to the overall performance of applications on microkernels. Through observing the register window mechanism, this study redesigns and implements the register bank mechanism, where the register window is allocated and managed by the kernel. Thus BankedIPC on SPARC is implemented. At the same time, as IPI underperforms on SPARC, FlexIPC is designed to optimize the performance of cross-core IPC. These approaches are employed to optimize the general synchronous IPC implemented on a self-developed microkernel ChCore. According to the test, the average IPC performance of microkernels on the optimized SPARC is about two times better with the application performance up to 15%.

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苏浩然,李文泰,古金宇,臧斌宇,陈海波,管海兵. SPARC架构下低时延微内核进程间通信设计.软件学报,,():1-19

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历史
  • 收稿日期:2023-04-03
  • 最后修改日期:2024-01-18
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  • 在线发布日期: 2024-06-14
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