In recent years, research on the interconnect technology of superconducting qubits has made important progress, providing an effective way to build a distributed computing architecture for superconducting quantum computers. The distributed superconducting architecture imposes strict constraints on the execution of quantum circuits in terms of network topology, qubit connectivity, and quantum state transfer protocols. To execute and schedule quantum circuits on a distributed architecture, the circuit mapping process is required to transform the quantum circuits to adapt to the underlying architecture and then to distribute the transformed circuits to multiple QPUs. The distributed circuit mapping process necessitates the insertion of additional quantum operations into the original circuit. Such operations, especially the inter-QPU state transfer operations, are susceptible to noise, leading to high error rates. Therefore, minimizing the number of such additional operations inserted by the mapping process is critical to improving the overall computation success rate. This study constructs an abstract model of distributed quantum computing based on the technical features of the interconnect technology of superconducting qubits and today’s superconducting QPUs. Moreover, this study proposes a distributed quantum circuit mapping approach based on this abstract model. The proposed approach consists of two main components the distributed qubit mapping algorithm and the qubit state routing algorithm. The former formulates the problem of distributing qubits to different QPUs as a combinatorial optimization problem and employs simulated annealing enhanced with local search to find the initial mapping that brings the optimal total routing cost. The latter constructs several heuristic qubit routing rules for different scenarios and integrates them systematically to minimize the additional operations inserted by the mapping process. The abstract model shields any technical details of the underlying architecture that are irrelevant to circuit mapping, which makes the mapping method applicable to a class of such networks rather than a specific one. Moreover, the approach proposed in this study can be used as an ancillary tool to design and evaluate the network topology of distributed systems. The experimental results show that, compared to the baseline approach, the proposed approach reduces the number of intra-chip operations (SWAP gates) and inter-chip operations (ST gates) by 69.69% and 85.88% on average, respectively, with a time overhead similar to existing algorithms.