The embedded system has been wildly applied in real-time automatic control systems, and most of these systems are safety-critical. For example, the engine control systems in an automobile, and the avionics in an airplane. It is very important to verify the schedulability property of such real-time embedded system in its early design stages, so that to avoid unexpected loss for the debugging of architecture design frictions. However, it has been proved to be a tough challenge to evaluate the schedulability of a PSRT (preemptive-scheduling real-time) system, especially when taking the constraints of system resources into consideration. The cache memory build inside the processor is such a kind of exclusive-accessing resource that is shared by all the tasks deployed on the processor. In addition, the CPRD (cache-related preemption delay) caused by preemptive task scheduling will bring extra time to the execution time to all the tasks. Thus, the CPRD should be taken into consideration when estimating the WCET (worst case executing time) of tasks in a real-time system. A model-based architecture level schedulability evaluate and verification method, which is designed for priority based PSRT system, is proposed in this study, in order to do cache resource constrained, and CPRD related schedulability evaluation based on AADL system architecture model. In the first step, the study enhances the property set of AADL storage elements, so that to be compatible with cache memory properties in system architecture model constructing. Secondly, the study proposes a set or algorithms to:estimate the CPRDs of a task before it is completed; do system schedule simulation and construct the schedule sequence with the constraint of Cache resource and CPRDs involved; and WCET estimation of the tasks in such a CPRD considered, preemptive-scheduling execution sequence. Finally, methods mentioned above are implemented within a prototype software toolkit, which is designed to do system level schedulability evaluation and verification with CPRD constraints considered. The toolkit is tested with a use case of aircraft airborne open-architecture intelligent information system. The result shows that, compared with schedule sequence constructed without cache memory resource constraints, the WCET estimated for most tasks are extended, and sequence order is changed. In some extreme cases, when CPRD is taken into consideration, some tasks are evaluated to be incompletable. The test shows that the method and algorithms proposed in this study are feasible.