网络处理器的分析与研究
作者:
基金项目:

Supported by the National Natural Science Foundation of China under Grant Nos.90104002, 60173012 (国家自然科学基金); the National High-Tech Research and Development Plan of China under Grant No.2001AA112080 (国家高技术研究发展计划); the National Grand Fundamental Research 9

  • 摘要
  • | |
  • 访问统计
  • |
  • 参考文献 [67]
  • |
  • 相似文献 [20]
  • |
  • 引证文献
  • | |
  • 文章评论
    摘要:

    目前,网络在提高链路速率的同时出现了大量的新协议及新服务,而传统的网络设备一般采用专用硬件芯片或者基于纯粹的软件方案,很难兼顾性能与灵活性两方面的要求.为此,一种并行可编程的网络处理器被引入到路由器(交换机)的处理层面.它基于ASIP技术对网络程序处理进行了优化,同时还兼有硬件和软件两种方案的特点.网络处理器的出现将经典的"存储-转发"结构变为"存储-处理-转发",这为复杂的QoS控制和负载处理提供了可能.从网络处理器本身及其应用两个角度出发,介绍了相关的研究工作,分析了系统特点和面临的挑战,并展望其未来的发展方向.

    Abstract:

    Nowadays the most salient trend with network is the increase in data rates while there is significant effort in developing new protocols and services. However, the traditional network devices which are custom logic based or pure software based, could hardly satisfy both performance and flexibility requirements. To overcome this obstacle, the parallel and programmable network processors have been involved into processing path of routers (switch). Besides network processors which are built on ASIP technology and optimized for network applications, possess the characteristic of hardware and software solution simultaneously. Network processors extend the classic store-and-forward pattern to store-process-and-forward, which makes room for complex QoS control and payload processing. In this paper, the related research work is introduced from two aspects, system and application, and the system issues and challenges of network processors are analyzed. In the end, the future evolution of network processors and associate researches are also speculated.

    参考文献
    [1]Shimonishi H, Murase T. A network processor architecture for flexible QoS control in very high-speed line interfaces. In: Proceedings of the 2001 IEEE Workshop on High Performance Switching and Routing (HPSR 2001). Dallas: IEEE Computer Society Press, 2001.402~406.
    [2]Blake S, Black D, Carlson M, Davies E, Wang Z, Weiss W. An architecture for differentiated services. IETF RFC 2475, 1998.
    [3]Floyd S, Jacobson V. Random early detection gateways for congestion control. IEEE/ACM Transactions on Networking, 1993, 1(4):397~413.
    [4]Thiele L, Chakraborty S, Gries M, Künzli S. Design space exploration of network processor architectures. In: Patrick C, et al., eds. Proceedings of the 8th International Symposium on High Performance Computer Architecture. Cambridge, MA: Morgan Kaufmann Publishers, 2002.
    [5]Wolf T, Franklin MA, Spitznagel E. Design tradeoffs for embedded network processors. Technical Report, WUCS-00-24, St. Louis: Department of Computer Science, Washington University, 2000.
    [6]Karlin S, Peterson L. VERA: an extensible router architecture. Computer Networks, 2002,38(3):277~293.
    [7]Wolf T, Franklin MA. CommBench-a telecommunica-tions benchmark for network processors. In: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software. Austin, TX, 2000. 154~162.
    [8]Hecht J. Wavelength division multiplexing.1999. http://www.technologyreview.com/articles/hecht0399.asp.
    [9]Memik G, Mangione-Smith B, Hu W. NetBench: a benchmarking suite for network processors. In: Proceedings of the International Conference on Computer-Aided Design (ICCAD). San Jose: IEEE Computer Society Press, 2001. 39~43.
    [10]Shah N. Understanding network processors [MS. Thesis]. Berkeley: Department of Electrical Engineering and Computer Sciences, University of California, 2001.
    [11]Nie XN, Gazsi L, Engel F, Fettweis G. A new network processor architecture for high-speed communications. In: Proceedings of the IEEE workshop on signal processing systems. IEEE Computer Society Press, 1999. 548~557.
    [12]McAuley A, Francis P. Fast routing table lookup using CAMs. In: Proceedings of the Infocom'93, Vol 3. IEEE Computer Society Press, 1993. 1382~1391.
    [13]Liu H. A trace driven study of packet level parallelism. In: Proceedings of the International Conference on Communications (ICC). New York, NY: IEEE Computer Society Press, 2002. 2191~2195.
    [14]IBM Corp. Rainier network processor. 2000. http://www.ibm.com/.
    [15]Intel Corp. Intel IXP1200 Network Processor. 2002. http://developer.intel.com/design/network/products/npfamily/ixp1200.htm.
    [16]Wolf T, Turner JS. Design Issues for High-performance active routers. IEEE Journal on Selected Areas in Communications, 2001, 19:404~409.
    [17]Kounavis ME, Campbell AT, Chou S, Modoux F, Vicente J, Zhuang H. The genesis kernel: a programming system for spawning network architectures. IEEE Journal on Selected Areas in Communications, 2001,19(3):511~526.
    [18]Wang J, Nahrstedt K. Parallel IP packet forwarding for tomorrow's IP routers. In: Proceedings of the 2001 IEEE Workshop on High Performance Switching and Routing (HPSR 2001). Dallas: IEEE Computer Society Press. 2001. 353~357.
    [19]Katavenis M, Sidiropoulos S, Courcoubetis C. Weighted round-robin cell multiplexing in a general-purpose ATM switch chip. IEEE Journal on Selected Areas in Communication, 1991,9(8):1265~1279.
    [20]Keutzer K. Enabling Fully Programmable Embedded System Solutions. Presentation. Gigascale Silicon Research Center Annual Review. 1999.
    [21]Network Processor Forum. http://www.npforum.org.
    [22]Network Processor Conference. http://www.networkprocessors.com.
    [23]Spalink T, Karlin S, Peterson L, Gottlieb Y. Building a robust software-based router using network processors. In: Proceedings of the 18th SOSP. ACM Press, 2001. 216~229.
    [24]Campbell AT, Chou ST, Kounavis ME, Stachtos VD. NetBind: a binding tool for constructing data paths in network processor-based routers. In: Proceedings of the 5th IEEE Conference on Open Architectures and Network Programming (OPENARCH). IEEE Computer Society Press. 2002. 91~103.
    [25]Thiele L, Chakraborty S, Gries M, Maxiaguine A, Greutert J. Embedded software in network processors models and algorithms. In: Proceedings of the 1st Workshop on Embedded Software. Lecture Notes in Computer Science 2211, Lake Tahoe, CA: Springer-Verlag, 2001. 416~434.
    [26]Qie X, Bavier A, Peterson L, Karlin S. Scheduling computations on a software-based router. In: Proceedings of the SIGMETRICS. IEEE Computer Society Press, 2001. 13~24.
    [27]Peterson L, Karlin S, Li K. OS support for general purpose routers. In: Proceedings of the 7th Workshop on Hot Topics in Operating Systems. IEEE Computer Society Press, 1999. 38~43.
    [28]Lahiri K, Raghunathan A, Dey S. System level performance analysis for designing on-chip communication architectures. IEEE Transactions on Computer Aided-Design of Integrated Circuits and Systems, 2001,20(6):768~783.
    [29]Peterson LL, Davie BS. Computer Networks: a System Approach. 2nd ed., Morgan Kaufmann Publisher, Inc., 2000.
    [30]Causey JW, Kim HS. Comparison of buffer allocation schemes in ATM switched: complete sharing, partial sharing and dedicated allocation. In: Proceedings of the International Conference on Communications. IEEE Computer Society Press, 1994. 1164~1168.
    [31]Jiang Y, Lin C, Wu J, Sun X. Integrated performance evaluation criteria for network traffic control. In: Proceedings of the IEEE Symposium on Computers and Communications. IEEE Computer Society Press, 2001. 438~443.
    [32]Shreedhar M, Varghese G. Efficient fair queueing using deficit round-robin. IEEE Transactions on Networking, 1996,4(3):375~ 385.
    [33]Lin C, Sheng L, Wu J, Xu MW. An integrative scheme of differentiated services. In: Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS 2000). IEEE Computer Society, 2000. 441~448.
    [34]Yong J, Kim YH. Performance analysis of a hybrid priority control scheme for input and output queueing ATM switches. In: Proceedings of the IEEE INFOCOM'98, Vol 3. IEEE Computer Society Press, 1998. 1470~1477.
    [35]Giessler A, Haanle J, Konig A, Pade E. Free buffer allocation-An investigation by simulation. Computer Networks, 1978,2: 191~204.
    [36]Casavant TL, Kuhl JG. A taxonomy of scheduling in general purpose distributed computing systems. IEEE Transactions on Software Engineering, 1988,14(2):141~154.
    [37]Eager DL, Lazowska ED, Zahorjan J. Adaptive load sharing in homogenous distributed systems. IEEE Transactions on Software Engineering, 1986,SE-12(5):662~675.
    [38]Barish G, Obraczka K. World wide web caching: trends and techniques. IEEE Communications Magazine, 2000,38(5):178~184.
    [39]Goldszmidt G, Hunt G. Scaling Internet services by dynamic allocation of connections. In: Proceedings of the 6th IFIP/IEEE International Symposium on Integrated Network Management. IEEE Computer Society Press, 1999. 24~28, 171~184.
    [40]Koufopavlou OG, Tantawy AN, Zitterbart M. Analysis of TCP/IP for high performance parallel implementations. In: Proceedings of the 17th IEEE Conference on Local Computer Networks. Minneapolis: IEEE Computer Society Press, 1992. 576~585.
    [41]Kencl L, Le Boudec J-Y. Adaptive load sharing for network processors. In: Proceedings of the IEEE INFOCOM 2002. IEEE Computer Society Press, 2002. 545~554.
    [42]Thaler DG, Ravishankar CV. Using name-based mappings to increase hit rates. IEEE/ACM Transactions on Networking, 1998,6(1): 1~14.
    [43]Pappu P, Wolf T. Scheduling processing resources in programmable routers. In: Proceedings of the IEEE INFOCOM 2002. IEEE Computer Society Press, 2002. 104~112.
    [44]Zhang H. Service disciplines for guaranteed performance service in packet switching networks. Proceedings of the IEEE, 1995, 83(10):1374~1396.
    [45]Parekh AK, Gallager RG. A generalized processor sharing approach to flow control: the single node case. In: Proceedings of IEEE INFOCOM'92. IEEE Computer Society Press, 1992. 915~924.
    [46]Bennett J, Zhang H. Worst case fair weighted fair queuing. In: Proceedings of the IEEE INFOCOM'95. IEEE Computer Society Press, 1995. 120~128.
    [47]Goyal P, Vin HM, Cheng HC. Start-Time fair queuing: a scheduling algorithm for integrated services packet switching networks. In: Proceedings of the ACM SIGCOMM. ACM Press, 1996. 157~168.
    [48]Bennett JCR, Zhang H. Hierarchial packet fair queuing algorithms. In: Proceedings of the ACM SIGCOMM. ACM Press, 1996. 43~56.
    [49]Golestani SJ. A self clocked fair queuing scheme for broadband applications. In: Proceedings of the IEEE INFOCOM'94. IEEE Computer Society Press, 1994. 636~646.
    [50]Wolf T, Franklin M. Locality-Aware predictive scheduling of network processors. In: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE Computer Society Press, 2001. 152~159.
    [51]Matsumoto C. Technical trial-by-fire awaits NPUs. EE Times. http://www.eetimes.com/story/OEG20011221S0027.
    [52]Nemirovsky A. Towards characterizing network processors: needs and challenges. XStream Logic, Whitepaper, 2000.
    [53]Tsai M, Kulkarni C, Sauer C, Shah N, Keutzer K. A benchmarking methodology for network processors. In: Patrick C, et al., eds. Workshop on Network Processors. Cambridge, MA: Morgan Kaufmann Publishers, 2002.
    [54]Standard Performance Evaluation Corporation (SPEC), http://www.spec.org/.
    [55]Weicker R. Dhrystone benchmark: rationale for version 2 and measurement rules. SIGPLAN Notices, 1988,23(8):1~2.
    [56]Lee C, Potkonjak M, Mangione-Smith W. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In: Proceedings of the International Symposium on Microarchitecture. IEEE Micro-30, IEEE Computer Society Press, 1997. 330~335.
    [57]Embedded Microprocessor Benchmark Consortium (EEMBC). http://www.eembc.org/.
    [58]Audenaert S, Chandra P. (NPF Benchmarking Working Group co-chairs), Network processors benchmark framework. NPF Benchmarking Workgroup, http://www.npforum.org/.
    [59]Burger D, Austin T. The simpleScalar tool set. Version 2.0. Technical Report, CS-TR-97-1342. University of Wisconsin, 1997.
    [60]Crowley P, Baer J-L. A modeling framework for network processor systems. In: Patrick C, et al., eds. Proceedings of the 8th International Symposium on High Performance Computer Architecture. Cambridge, MA: University of Washington, 2002.
    [61]Mathew J. IBM ropes in partners for network processors. Electronic News Online. 2000. http://www.e-insite.net/electronicnews/ index.asp?layout=article&articleId=CA49443.
    [62]Matthew J. Network processor companies face the same tough issues. Electronic News Online. 2000. http://www.e-insite.net/ electronicnews/index.asp?layout=article&articleId=CA49900.
    [63]Matsumoto C. CloudShield pushes net processors to next performance level. EE Times. 2001. http://www.eetimes.com/story/ OEG20010625S0088.
    [64]Austin TX, Wilmington MA. Motorola's C-Port network processor chosen as key technology in the hammer packetSphere platform from empirix. 2001. http://apspg.motorola.com/press/022801/cport.html.
    [65]Atondo A. Fabless semiconductor start-up SiByte announces breakthrough MIPS64 microprocessor core--delivers up to 1 GHz at less than 2.5 Watts world's most power-efficient core in its performance class. Press Release, http://www.sibyte.com /pressroom/ docs/pr_20000612_sb1.html.
    [66]van Eijndhoven JTJ, Sijstermans FW, Vissers KA, Pol EJD, Tromp MJA, Struik P, Bloks RHJ, van der Wolf RHJ, Pimentel AD, Vranken HPE. TriMedia CPU64 Architecture. In: Proceedings of the International Conference on Computer Design (ICCD'99). Austin: IEEE Computer Society Press, 1999. 586~592.
    [67]Hekstra GJ, La Hei GD, Bingley P, Sijstermans FW. TriMedia CPU64 design space exploration. In: Proceedings of the International Conference on Computer Design (ICCD'99). Austin: IEEE Computer Society Press, 1999. 599~607.
    网友评论
    网友评论
    分享到微博
    发 布
引用本文

谭章熹,林闯,任丰源,周文江.网络处理器的分析与研究.软件学报,2003,14(2):253-267

复制
分享
文章指标
  • 点击次数:8367
  • 下载次数: 9109
  • HTML阅读次数: 0
  • 引用次数: 0
历史
  • 收稿日期:2002-08-09
  • 最后修改日期:2002-11-12
文章二维码
您是第19728422位访问者
版权所有:中国科学院软件研究所 京ICP备05046678号-3
地址:北京市海淀区中关村南四街4号,邮政编码:100190
电话:010-62562563 传真:010-62562533 Email:jos@iscas.ac.cn
技术支持:北京勤云科技发展有限公司

京公网安备 11040202500063号