This paper presents a module silicon compilation expert system--SCES developed by us. SCES consists of a set of cooperating expert systems with common blackboard structures and is featured by performing topological modification, using widespreadly deducing CAD database (dCADB), logical reduces, rule_based programming and an open inference schedule system. SCES takes specifications (chip dimension rate, cell delays and pad arrangements) from input file, performs topological modifications, logical and layout automatic design,sets up dCABs of design results,outputs the logic drawing,layout and circuit SPICE format file including parasitic parameters of interconnections.