面向CPU-GPU平台的HEVC编码器优化
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国家高技术研究发展计划(863)(2015AA015903);国家自然科学基金(61322106, 61272255);深圳市孔雀计划;北京市优秀博士学位论文导师奖资助项目(20128000103)


HEVC Encoder Optimization for CPU-GPU Platform
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    摘要:

    针对CPU-GPU平台提供了一种能显著降低高效视频编码(high efficiency video coding,简称HEVC)复杂度的优化方案.根据编码器的复杂度分布及不同模块的特点,针对帧内预测、帧间预测以及环路滤波分别进行了优化.在帧内预测中,基于相邻编码单元(coding unit,简称CU)之间的相关性,提出了一种CU的深度决策方法以及一种减少率失真优化(RDO)的模式数量的方法,降低了帧内编码的复杂度.在帧间预测中,提出将耗时最大的运动估计模块完善在图形处理单元(GPU)上,通过中央处理单元(CPU)和GPU的流水线工作获得了明显的加速,并基于预测残差的能量提出了一种编码单元提前终止划分的方法,有效降低了帧间编码复杂度.在环路滤波中,提出了一种GPU端的自适应样本点补偿(sample adaptive offset,简称SAO)参数决策方法及去块滤波方法,有效分担了CPU端的复杂度.上述优化实现在HM16.2上,实验结果表明,提出的优化方案可以获得高达68%的编码复杂度节省,而平均性能损失仅为0.5%.

    Abstract:

    This paper provides a comprehensive optimization strategy aiming at reducing the complexity of high efficiency video coding (HEVC) encoder with CPU-GPU cooperation. Based on the computational complexity distribution of HEVC encoder and characteristics of different modules and coding tools, intra coding, inter coding and in-loop filtering are collaboratively optimized. For intra coding, based on the correlation between neighboring coding units (CUs), depth range of CU is predicted and the number of candidates in intra mode candidate set for RDO (rate distortion optimization) is cut down, to avoid unnecessary computations. For inter coding, the most time consuming module, motion estimation (ME), is implemented with the collaboration of CPU and GPU in pipeline. Based on the energy of prediction residuals, an early termination scheme of CU splitting is proposed in this paper. For in-loop filtering, GPU based sample adaptive offset (SAO) parameter decision scheme and GPU based deblocking scheme are proposed to further reduce the coding complexity on CPU. The overall optimization scheme is implemented on the HM 16.2 platform, and experiments demonstrate that the proposed optimization scheme can reduce over 68% of the coding complexity of HEVC encoder, with only 0.5% performance loss in average.

    参考文献
    [1] Sullivan GJ, Ohm JR, Han WJ, Wiegand T. Overview of the high efficiency video coding (HEVC) standard. IEEE Trans. on Circuits System for Video Technology, 2012,22(12):1649-1668.
    [2] Ohm JR, Sullivan GJ, Schwarz H, Tan TK, Wiegand T. Comparison of the coding efficiency of video coding standards-including high efficiency video coding (HEVC). IEEE Trans. on Circuits and Systems for Video Technology, 2012,22(12):1669-1684.
    [3] Lainema J, Bossen F, Han WJ, Min J. Intra coding of the HEVC standard. IEEE Trans. on Circuits and Systems for Video Technology, 2012,22(12):1792-1801.
    [4] Zhao L, Zhang L, Ma S, Zhao D. Fast mode decision algorithm for intra prediction in HEVC. In:Proc. of the IEEE Visual Communications and Image Processing (VCIP). 2011. 1-4.
    [5] Jiang W, Ma H, Chen Y. Gradient based fast mode decision algorithm for intra prediction in HEVC. In:Proc. of the Consumer Electronics, Communications and Networks (CECNet). Three Gorges, 2012. 1836-1840.
    [6] Shen L, Zhang Z, An P. Fast CU size decision and mode decision algorithm for HEVC intra coding. IEEE Trans. on Consumer Electronics, 2013,59(1):207-213.
    [7] Wang S, Ma S, Wang S, Zhao D, Gao W. Fast multi reference frame motion estimation for high efficiency video coding. In:Proc. of the 20th Int'l Conf. on Image Processing (ICIP). Melbourne, 2013. 2005-2009.
    [8] Hsu WJ, Hang HM. Fast coding unit decision algorithm for HEVC. In:Proc. of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conf. (APSIPA). Kaohsiung, 2013. 1-5.
    [9] Yu Q, Zhang X, Wang S, Ma S. Early termination of coding unit splitting for HEVC. In:Proc. of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conf. (APSIPA). Hollywood, 2012. 1-4.
    [10] Correa G, Assuncao P, Agostini L, Cruz L. Complexity control of high efficiency video encoders for power-constrained devices. IEEE Trans. on Consumer Electronics, 2011,57(4):1866-1874.
    [11] NVIDIA. CUDA C Programming Guide. Version 6.5, 2014. http://docs.nvidia.com/cuda/cuda-c-programming-guide
    [12] Wang XW, Song L, Chen M, Yang JJ. Paralleling variable block size motion estimation of HEVC on CPU plus GPU platform. In:Proc. of the IEEE Int'l Conf. on Multimedia and Expo Workshops (ICMEW). San Jose, 2013, 1-5.
    [13] Kim S, Lee D, Sohn C, Oh S. Fast motion estimation for HEVC with adaptive range decision on CPU and GPU. In:Proc. of the 2nd IEEE China Summit and Int'l Conf. on Signal and Information Processing (ChinaSIP). Xi'an, 2014. 349-353.
    [14] Radicke S, Hahn J, Grecos C, Wang Q. A highly-parallel approach on motion estimation for high efficiency video coding (HEVC). In:Proc. of the IEEE Int'l Conf. on Consumer Electronics (ICCE). Las Vegas, 2014. 187-188.
    [15] Ma JC, Luo FL, Wang SS, Ma SW. Flexible CTU-level parallel motion estimation by CPU and GPU pipeline for HEVC. In:Proc. of the IEEE Int'l Conf. on Visual Communications and Image Processing (VCIP). Valletta, 2014. 14-17.
    [16] Luo FL, Ma SW, Ma JC, Qi HG, Su L, Gao W. Multiple layer parallel motion estimation on GPU for high efficiency video coding (HEVC). In:Proc. of the IEEE Int'l Symp. on Circuits and Systems (ISCAS). Lisbon, 2015. 1122-1125.
    [17] Wang Y, Fan XP, Zhao L, Ma SW. A fast intra coding algorithm for HEVC. In:Proc. of the 2014 IEEE Int'l Conf. on Image Processing (ICIP). Paris, 2014. 4117-4121.
    [18] Bjøntegaard G. Improvement of BD-PSNR model. VCEG-AI11, Berlin, 2008.
    [19] 马思伟.新一代高效视频编码标准HEVC的技术架构.中国多媒体通信,2013,(7):20-21.
    [20] 沈燕飞,李锦涛,朱珍民,张勇东.高效视频编码.计算机学报,2013,36(11):2340-2355.
    [21] 雷海军,杨忠旺,陈骁,袁梅冷.一种快速HEVC编码单元决策算法.计算机工程,2014,(3):270-273.
    [22] 王超超,王万良,岑跃峰,姚信威,姚晓敏.HEVC快速编码深度选择算法.计算机工程与应用,2014.
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罗法蕾,王苫社,马俊铖,马思伟,高文.面向CPU-GPU平台的HEVC编码器优化.软件学报,2015,26(S2):239-246

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  • 收稿日期:2015-05-15
  • 最后修改日期:2015-10-12
  • 在线发布日期: 2016-01-11
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