Simulation-Based verification approaches need a large amount of test vectors for verifying the corner case of designs. This paper proposes a novel assertion-based automatic functional vectors generation method which takes assertion as the functional coverage metric. For the given assertion, the related design part is first extracted, and then the assertion property and the signal propagation process based on the DD model is converted to the CLP constraints; Finally, functional vectors are generated by solving the constraints. The advantage of this method is the combination of the program slicing based design extraction, the word-level SAT engine, and the dynamic search techniques. The method can deal with large designs and handle control and datapath design in a unified framework. Experimental results show that the method is efficient for finding the design errors and vectors generation.