To verify the correctness of the RTL(register transfer level) result got from th e high level synthesis, an algorithm of DFG(data flow graph) invert extracting i s designed and realized in this paper. Four sections are included in this algori thm: analyze FSM(finite state machine) dynamically and obtain control signal; se arch the active component for current states of FSM and convert the operate note of DFG from the structure of data path; analyze the relationship between the no tes of DFG, separate the variables sharing the same register.