| 崔进,段振华,田聪,张南.一种嵌套中断系统的建模和分析方法.软件学报,2018,29(6):1670-1680 |
| 一种嵌套中断系统的建模和分析方法 |
| Modeling and Analysis of Nested Interrupt Systems |
| 投稿时间：2017-07-06 修订日期：2017-09-01 |
| DOI：10.13328/j.cnki.jos.005472 |
| 中文关键词: 嵌套中断系统 投影时序逻辑 MSVL (modeling,simulation and verification language) 形式化建模与验证 |
| 英文关键词:nested interrupt systems projection temporal logic MSVL (modeling, simulation and verification language) formal modeling and verification |
| 基金项目:国家自然科学基金（61420106004，61732013，61572386） |
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| 摘要点击次数: 964 |
| 全文下载次数: 620 |
| 中文摘要: |
| 在嵌入式系统和各类操作系统中，中断机制是确保实时响应各类异步事件的重要方法.通常在处理一个中断事件的过程中，往往会有更紧迫的中断事件请求响应，因而发生中断嵌套.建模并验证嵌套中断系统是具有挑战性的工作.提出一种建模和验证嵌套中断系统的方法.首先，提出基于投影时序逻辑（projection temporal logic，简称PTL）的定义，并将这种定义推广到包含任意多中断事件的中断系统上，从而得出嵌套中断系统基于投影时序逻辑的形式化模型；其次，使用投影时序逻辑定义的基本中断语句扩充建模仿真和验证语言（modeling，simulation andverification language，简称MSVL），并扩展MSVL语言的解释器，使其可以对嵌套中断系统进行建模仿真和验证；最后，通过一个实例展现所提出方法的正确性和实用性. |
| 英文摘要: |
| The interrupt mechanism is a commonly used means to ensure real-time response to various asynchronous events in embedded systems and various real-time operating systems. Nested interrupts are likely to occur when the request of more urgent interrupt event arise while processing a less urgent one. Modeling and verifying such systems are challenging tasks. This paper proposes an approach to modeling and verifying systems with nested interrupts. First, MSVL (modeling, simulation and verification language) is extended to model such systems by defining an interrupt statement using projection temporal logic (PTL). Then, methods of modeling different nested interrupt systems using the interrupt statement are studied. Next, the MSV toolkit is extended to model, simulate, and verify MSVL programs with nested interrupts automatically. Finally, a case study is given to demonstrate how the proposed method works. |
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