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论域理论在超大规模集成电路逻辑设计上的运用 
An Application of Domain Theory to Logical Design of VLSI Circuits 
投稿时间：19980901 修订日期：19981224 
DOI： 
中文关键词: 大规模集成电路，逻辑门，Kleene三值逻辑，全半序，普通不动点算子，单调性. 
英文关键词:VLSI circuit, logic gate, Kleene 3valued logic, Complete Partial Order (CPO), general fixpoint operator, monotonicity. 
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中文摘要: 
认为传统的二值布尔不利于大规模集成电路的设计，尤其是在逻辑门电路上.为此引入了三值逻辑.此三值逻辑是基于集成电路的物理性质，且碰巧等同于Kleene的三值逻辑.鉴于Kleene三值逻辑的不完备性，文章将论域理论以及普通不动点算子运用于此，使三值逻辑获得此逻辑系统的单调完备性定理.文章认为这个结果有利于集成电路设计的可靠性，具有广阔的应用前景. 
英文摘要: 
This paper is to suggest that traditional 2valued Boolean algebra is not sufficient for representation of VLSI circuits at logic gate level, although it is the case for combinational circuits. Instead of using the RegisterandTransfer technique at RT level to represent sequential circuits, an alternative is sought and found. That is, all uncertain voltages such as oscillations and floating voltages are identified by the same value, denoted as ⊥ (called bottom). The two certain voltages are, as usual,ground and power; they are denoted by 0 and 1 respectively. An invertor, a norgate and a nandgate are defined according to the physics of VLSI circuits instead of the Boolean algebra. As a result, a logic is obtained which coincides with Kleene 3valued logic provided that Kleene's u=⊥. As it is well known, Kleene 3valued logic is functionally incomplete. This means that not every function (or gate) can be constructed from invertors, norgates and nandgates. However, by introducing a partial order into the logic, by using general fixedpoint operators instead of the least fixpoint operator to deal with feedbacks in VLSI circuits, and by applying CPO (complete partial order) domain theory to the derived 3valued logic system, the result obtained means that this system is functionally monotonic complete. Also, the canonical normal forms for this Kleene 3valued logic are obtained. Although the present results are mainly semantic, it is very interesting in pursuing the research further by investigating the syntactical derivability. Such research would derive more secure circuits close to reality, which is to make the work compatible with VHDL, Verilog HDL and/or EDIF. Incidentally, Mukaidono has obtained similar results, although his approach is not as coherent as the one presented in this paper. 
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