主页期刊介绍编委会编辑部服务介绍道德声明在线审稿编委办公English
2020-2021年专刊出版计划 微信服务介绍 最新一期:2020年第10期
     
在线出版
各期目录
纸质出版
分辑系列
论文检索
论文排行
综述文章
专刊文章
美文分享
各期封面
E-mail Alerts
RSS
旧版入口
中国科学院软件研究所
  
投稿指南 问题解答 下载区 收费标准 在线投稿
孙踊,胡易.论域理论在超大规模集成电路逻辑设计上的运用.软件学报,2000,11(5):569-583
论域理论在超大规模集成电路逻辑设计上的运用
An Application of Domain Theory to Logical Design of VLSI Circuits
投稿时间:1998-09-01  修订日期:1998-12-24
DOI:
中文关键词:  大规模集成电路,逻辑门,Kleene三值逻辑,全半序,普通不动点算子,单调性.
英文关键词:VLSI circuit, logic gate, Kleene 3-valued logic, Complete Partial Order (CPO), general fixpoint operator, monotonicity.
基金项目:
作者单位
孙踊 贝尔法斯特女王大学计算机科学系,英国 
胡易 集成化系统公司,英国 
摘要点击次数: 3184
全文下载次数: 2937
中文摘要:
      认为传统的二值布尔不利于大规模集成电路的设计,尤其是在逻辑门电路上.为此引入了三值逻辑.此三值逻辑是基于集成电路的物理性质,且碰巧等同于Kleene的三值逻辑.鉴于Kleene三值逻辑的不完备性,文章将论域理论以及普通不动点算子运用于此,使三值逻辑获得此逻辑系统的单调完备性定理.文章认为这个结果有利于集成电路设计的可靠性,具有广阔的应用前景.
英文摘要:
      This paper is to suggest that traditional 2-valued Boolean algebra is not sufficient for representation of VLSI circuits at logic gate level, although it is the case for combinational circuits. Instead of using the Register-and-Transfer technique at RT level to represent sequential circuits, an alternative is sought and found. That is, all uncertain voltages such as oscillations and floating voltages are identified by the same value, denoted as ⊥ (called bottom). The two certain voltages are, as usual,ground and power; they are denoted by 0 and 1 respectively. An invertor, a nor-gate and a nand-gate are defined according to the physics of VLSI circuits instead of the Boolean algebra. As a result, a logic is obtained which coincides with Kleene 3-valued logic provided that Kleene's u=⊥. As it is well known, Kleene 3-valued logic is functionally incomplete. This means that not every function (or gate) can be constructed from invertors, nor-gates and nand-gates. However, by introducing a partial order  into the logic, by using general fixed-point operators instead of the least fixpoint operator to deal with feedbacks in VLSI circuits, and by applying CPO (complete partial order) domain theory to the derived 3-valued logic system, the result obtained means that this system is functionally monotonic complete. Also, the canonical normal forms for this Kleene 3-valued logic are obtained. Although the present results are mainly semantic, it is very interesting in pursuing the research further by investigating the syntactical derivability. Such research would derive more secure circuits close to reality, which is to make the work compatible with VHDL, Verilog HDL and/or EDIF. Incidentally, Mukaidono has obtained similar results, although his approach is not as coherent as the one presented in this paper.
HTML  下载PDF全文  查看/发表评论  下载PDF阅读器
 

京公网安备 11040202500064号

主办单位:中国科学院软件研究所 中国计算机学会 京ICP备05046678号-4
编辑部电话:+86-10-62562563 E-mail: jos@iscas.ac.cn
Copyright 中国科学院软件研究所《软件学报》版权所有 All Rights Reserved
本刊全文数据库版权所有,未经许可,不得转载,本刊保留追究法律责任的权利