The interrupt mechanism is a commonly used means to ensure real-time response to various asynchronous events in embedded systems and various real-time operating systems. Nested interrupts are likely to occur when the request of more urgent interrupt event arise while processing a less urgent one. Modeling and verifying such systems are challenging tasks. This paper proposes an approach to modeling and verifying systems with nested interrupts. First, MSVL (modeling, simulation and verification language) is extended to model such systems by defining an interrupt statement using projection temporal logic (PTL). Then, methods of modeling different nested interrupt systems using the interrupt statement are studied. Next, the MSV toolkit is extended to model, simulate, and verify MSVL programs with nested interrupts automatically. Finally, a case study is given to demonstrate how the proposed method works.