As a key component of virtualization technology, memory virtualization directly affects the performance of virtual machines. However, the current memory virtualization methods always tradeoff between the overhead of two-dimensional address translation and the overhead of page table synchronization. The traditional shadow paging method uses an extra page table maintained by software to achieve the native address translation performance. But the synchronization of shadow page table based on write protection always causes VM-exits, which seriously decreases the performance. The nested paging method uses hardware-assisted virtualization, and the process page table of applications and the nested page table of the VM can be directly loaded into the MMU, thus avoiding the overhead of page table synchronization, but the two-dimensional page table traversal will seriously degrade the address translation performance. Based on the privilege model and hardware features under RISC-V architecture, this paper present Lazy Shadow Paging(LSP), which reduces the overhead of page table synchronization while maintaining the efficiency of address translation of shadow page tables. The lazy shadow paging first analyzes the access characteristics of process page table pages by guest OS, and combines the synchronization with the TLB flush. It then delays the synchronization software overhead to the first visit after that. At the same time, lazy shadow paging designs a fast path for VM-exits based on the privilege level model under RISC-V. Experiments show that under the basic RISC-V architecture, the lazy shadow paging is reduced 50% of the VM-exits compared with the traditional shadow paging in the micro-benchmark. For the typical application in SPEC2006 benchmark, the lazy shadow paging reduces the number of VM-exits by up to 25% compared with the traditional shadow paging, and reduces 12 memory accesses per TLB miss compared with the nested paging.