Cache simulators play an indispensable role in exploring cache architectures and researching cache side channels. Spike, as the standard implementation of the RISC-V instruction set, provides a complete environment for cache research based on RISC-V. However, Spike’s cache model has several issues, including low simulation granularity and significant differences from the cache structures of real processors. To address these issues, this paper modifies and extends Spike’s cache model, naming the modified version FlexiCAS (Flexible Cache Architectural Simulator), and refers to the modified Spike as Spike-FlexiCAS. FlexiCAS supports various cache architectures, featuring flexible configuration and easy extensibility, and allows arbitrary combinations of cache features, such as coherence protocols and implementation methods. Additionally, FlexiCAS can simulate cache behavior independently of Spike.The performance test results show that FlexiCAS has a significant performance advantage over the cache model of the currently fastest execution-driven simulator, ZSim.